Generally a number of semiconductor devices are simultaneously formed on a semiconductor wafer by, for example, a technique of precisely transferring photographs. Thereafter, the semiconductor wafer is cut along scribe lines and semiconductor devices formed on the semiconductor wafer are split as semiconductor chips.
Conventional inspections conducted in a process of manufacturing the semiconductor device include, for example, inspections of electrical characteristics. Some inspections of electrical characteristics are conducted before a plurality of semiconductor devices formed on the semiconductor wafer are split into semiconductor chips, and others are conducted after the split semiconductor chips are packaged. The electrical characteristics of semiconductor devices before splitting are inspected using a so-called wafer prober and tester. The electrical characteristics of packaged semiconductor devices are inspected using a so-called handler and tester.
In the process of manufacturing semiconductor devices, it is necessary to maintain high yields in the inspections to reduce manufacturing costs. Thus, when the yields decrease, it is necessary to immediately identify the cause. This process is generally called defect analysis, which needs to be promptly performed with precision.
Semiconductor devices are broadly classified as logic circuits and analog circuits. The logic circuit mainly realizes a digital function and the input and output of the logic circuit are binary and represented as Low or High.
General defect analysis performed on the logic circuit includes a technique called “defect classification.” In defect classification, a defect category is set for each defect pattern, each defect category is numbered according to inspection contents, and defects are classified into defect categories and are compiled.
Defect patterns (electrical characteristics) occurring on logic circuits are mainly caused by an open defect (a break in fine wiring in a semiconductor chip) and a short (a short circuit in fine wiring in a semiconductor chip). Hence, the cause of a defect can be tracked down with relative ease and the cause can be tracked down in the manufacturing process to a certain degree by the foregoing defect classification.
In contrast to the logic circuit, inspections on analog circuits are quite different from those of logic circuits in that a technique called a “finished quality evaluation” is used to evaluate the performance of completed semiconductor devices. This technique evaluates the performance of semiconductor devices on evaluation items such as an amplification factor, noise, and a frequency characteristic. In this technique, when a circuit completed as a semiconductor device does not reach an acceptance criteria, the semiconductor device is judged to be defective. In the following explanation, a defect judged due to insufficient performance is referred to as a “finished quality defect.” The finished quality defect is a major factor responsible for reduced yields in the analog circuit.
Hence, when a semiconductor device is constituted only of analog circuits, a technique called “rank sorting” is used. In the rank sorting, regarding semiconductor devices of analog circuits, performance such as an amplification factor, noise, and frequency characteristics is measured. The semiconductor devices are classified into ranks according to the performance and are shipped for each rank.
Listed below are Japanese unexamined patent application publications available as prior art documents:    1. Japanese Patent Laid-Open No. 2000-306395    2. Japanese Patent Laid-Open No. 11-8327    3. Japanese Patent Laid-Open No. 11-26333
However, semiconductor devices in large scale integration and one-chip configurations have been developed in recent years. The one-chip configuration includes a digital semiconductor and an analog semiconductor as a single semiconductor device unlike the conventional art, in which a digital semiconductor and an analog semiconductor are combined with each other. Thus, the one-chip configuration has a digital circuit and an analog circuit on the same semiconductor device.
Particularly due to the recent development of digital products, an analog circuit is frequently integrated into a semiconductor device of a digital circuit. In this case, it is difficult to measure the performance of the analog circuit alone and thus rank sorting cannot be performed in the above manner before shipping. Further, even when a digital circuit is acceptable, an analog circuit evaluated as a “finished quality defect” results in a defective semiconductor device, thereby reducing yields. For this reason, it is necessary to reduce a performance error required for analog circuits in order to increase yields.
Unlike the digital circuit, the analog circuit has an input and output of linear values and thus when “defect classification”used for defect analysis of the digital circuit is used for defect analysis on a semiconductor device including both of a digital circuit and an analog circuit, the following problems arise:
First, it is not possible to read the measurement values of electrical characteristics in the analog circuit. Generally inspections on linear values have inspection specifications of a lower limit specification, a central specification, and an upper limit specification. An inspection result is obtained by deciding a specification corresponding to a measurement value. However, when measurement values cannot be read, it is not possible to recognize whether the performance of the analog circuit is deviated to the lower limit or the upper limit.
Second, since measurement values cannot be read during inspection, when a defect is found in inspection results, it is not possible to recognize how far the measurement value is deviated from the inspection specifications. Thus, it is not possible to distinguish, from inspection results, whether the defect is a finished quality defect or an open defect or short circuit.
Further, the following is known: in inspections on electrical characteristics, electrical characteristics vary from position to position in the plane of a semiconductor wafer in some cases, causing variations in measurement value. However, it is not possible to read from defect categories what electrical characteristics are obtained on which position in the plane of the semiconductor wafer, that is, variations in electrical characteristics in the plane of the wafer.
For example, after semiconductor devices on a semiconductor wafer are split into semiconductor chips, when one of the semiconductor chips is found to be a finished quality defect during inspections, the following information cannot be read: to what degree the semiconductor chip, which has been found to be a finished quality defect, is defective in terms of measurement values of inspections, and information about whether a measurement value close to the lower limit specification or the upper limit specification is actually found on a semiconductor chip around the defective semiconductor chip on the semiconductor wafer where the semiconductor chips are cut, even if a finished quality defect is not found.
Therefore, in the conventional technique, when semiconductor devices decrease in yield, it is difficult to readily recognize whether yields are accidentally reduced or signs pointing to lower yields have been already exhibited. For example, one of the signs is that a measurement value are within the inspection specifications but gradually comes closer to the lower limit specification or the upper limit specification.
Further, inspections on electrical characteristics generally have several tens to hundreds inspection items and several tens to hundreds semiconductor devices are formed on a semiconductor wafer. Thus, the number of inspection items multiplied by the number of semiconductor devices makes an enormous amount of data which is collected as inspection results of electrical characteristics.
For this reason, when the inspection results on electrical characteristics are displayed simply as numeric data, it is difficult for an evaluator to use the data for defect analysis. When result values indicating inspection results are collected but position information, which indicates where a semiconductor device to be inspected is disposed in the plane of a semiconductor wafer, is hard to understand, the evaluator cannot readily perform defect analysis. Moreover, it is not possible to recognize the distribution tendency of electrical characteristics in a semiconductor wafer before splitting.
Hence, a defect analysis system is demanded which simultaneously displays position information on semiconductor devices in the plane of a semiconductor wafer and result values indicating the inspection results of finished quality evaluations to communicate the inspection results clearly to the evaluator who performs defect analysis. Further, instead of defect classification (defect category data), defect analysis according to the measurement values of electrical characteristics is necessary to confirm finished quality.